Stage conception RTL ASIC (H/F) à Nice

Atos SE (Societas Europaea) is a leader in digital services with pro forma annual revenue of circa € 12 billion and circa 100,000 employees in 72 countries. Serving a global client base, the Group provides Consulting & Systems Integration services, Managed Services & BPO, Cloud operations, Big Data & Cyber-security solutions, as well as transactional services through Worldline, the European leader in the payments and transactional services industry. With its deep technology expertise and industry knowledge, the Group works with clients across different business sectors: Defense, Financial Services, Health, Manufacturing, Media, Utilities, Public sector, Retail, Telecommunications, and Transportation.

Atos is focused on business technology that powers progress and helps organizations to create their firm of the future. The Group is the Worldwide Information Technology Partner for the Olympic & Paralympic Games and is listed on the Euronext Paris market. Atos operates under the brands Atos, Atos Consulting, Atos Worldgrid, Bull, Canopy, Unify and Worldline.

The increasing complexity of integrated circuits considerably extends development time (design, verification, etc.). The use of IP (generic modules) in the design is a way to reduce this development time. ATOS currently has several IP: fifos, arbiters, DMA... In a process of continuous improvement, ATOS continue to improve & increase its IP library.
During your internship, your main tasks will be:
- Review of IP design rules (naming conventions, generic design, use of parameters, etc.)
- Definition and writing of the specification
- Coding in SystemVerilog
- Writing basic testbenchs for validation
- Presentation and training on the IP developed for design and verification teams
You will have to use your communication skills as you will interact with ASIC's design teams (logical design, verification), and you will use the most advanced EDA tool and flow.

Your Application
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