Ingénieur Conception logique ASIC H/F à Nice

Atos is a global leader in digital transformation with approximately 100,000 employees in 72 countries and annual revenue of around € 12 billion. The European number one in Big Data, Cybersecurity, High Performance Computing and Digital Workplace, The Group provides Cloud services, Infrastructure & Data Management, Business & Platform solutions, as well as transactional services through Worldline, the European leader in the payment industry. With its cutting-edge technologies, digital expertise and industry knowledge, Atos supports the digital transformation of its clients across various business sectors: Defense, Financial Services, Health, Manufacturing, Media, Energy & Utilities, Public sector, Retail, Telecommunications and Transportation. The Group is the Worldwide Information Technology Partner for the Olympic & Paralympic Games and operates under the brands Atos, Atos Consulting, Atos Worldgrid, Bull, Canopy, Unify and Worldline. Atos SE (Societas Europaea) is listed on the CAC40 Paris stock index. For more information, visit: atos.net

As a digital IC Design Engineer, you will be integrated in the ASIC department of ATOS R&D. The department is in charge of dedicated ASIC design for all Bull systems including interconnect for HPC, node controller for big memory systems. Your primary responsibility will be RTL design. The main tasks are:

• Define the high-level architecture and the micro-architecture of these components
• Write the functional specification of subsets of the circuit
• Write RTL description (Verilog, SystemVerilog)
• Cooperate with the team to ensure a good integration up to the top level
• Interact with verification team (test plans definition, corrections RTL)
• Collaborate with the physical design team (timing, physical constraints, floorplan)
• Prepare and participate to the bring-up of 1^st samples

Required Skills:

- Seven years or more experience of digital RTL design experience, SystemVerilog preferred

- Multiprocessor computer systems architecture, High speed serial link

- Knowledge of digital logic design best practices

- Detailed understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, and equivalence checking
- Understanding of Design Verification and the ability to write self-checking test suites and debug/triage failures

- Knowledge of a scripting language such as Perl, Tcl, Python

- Fluent English (written and oral)

- Autonomy, rigorous, dynamism and team spirit

Knowledge of one or more of the following topics would be appreciated:

- System On Chip or Network On Chip

- Modeling

- Prototyping

- FPGA

- Communication bus (AMBA / AHB / AXI / PCIe)

Education : Engineering graduate in micro-electronics or in computer design

Experience: Minimum of 7 years required in ASIC design

At Atos, diversity is at the heart of our HR policy. This is why Atos has put in place an agreement on gender equality. In addition, our businesses are all accessible to people with disabilities, regardless of the nature of their disability.